1. Field of the Invention
The present invention relates to the prevention of a short circuit in a semiconductor device.
2. Description of the Background Art
FIG. 43A shows the structure of a background art semiconductor device. The surface of a semiconductor substrate 1 is divided into two regions: an element isolation region 2 in which an isolation element 2a employing the LOCOS process or a trench is formed; and an active region 3 in which MOS structure elements and the like are formed. A gate insulation film 5a is formed on the surface of the isolation element 2a, and an interconnect line 4a is formed on the gate insulation film 5a. Sidewalls 6a are formed on the side faces of the interconnect line 4a. Gate insulation films 5b are formed on the surface of the active region 3, and gate electrodes 4b are formed on the respective gate insulation films 5b. Sidewalls 6b are formed on the side faces of each of the gate electrodes 4b. Source and drain regions which constitute a MOS structure element with each of the gate insulation films 5b and each of the gate electrodes 4b are formed in the active region 3, but are not shown in FIG. 43A for purposes of simplicity. The gate insulation film 5a under the interconnect line 4a is shown as formed at the same time as the gate insulation films 5b, but is not required functionally.
An interlayer insulation film 7 is once formed to cover the entire top surface of the above described structure. Then, a contact hole 8a is formed in the interlayer insulation film 7 over the element isolation region 2 for electrical connection to the interconnect line 4a, and contact holes 8b are formed in the interlayer insulation film 7 over the active region 3 for electrical connection to the source and drain regions (not shown). The contact holes 8a and 8b are filled with a conductive material for contact later.
In the structure of the semiconductor device as above described, the contact holes 8a and 8b are not formed as designed in some cases. This is prone to occur, for example, when the photolithographic technique is used to form the contact holes 8a and 8b.
FIG. 43B shows the structure of the background art semiconductor device when the contact holes 8a and 8b are shifted slightly leftwardly in cross-section from the designed position as the result of an insufficient photomask alignment precision during manufacturing the structure of FIG. 43A, for example. In other cases, insufficient contact between a photomask and a photoresist precludes the pattern of the photomask from being correctly transferred to the photoresist, resulting in insufficient dimension control of the diameter of the contact holes. FIG. 43C shows that the contact holes 8a and 8b have excessively large diameters, for example.
If the contact holes are thus not positioned as designed, a short circuit occurs in a portion of the semiconductor device which should not be short-circuited. For example, as shown in FIGS. 43B and 43C, since the gate electrodes 4b are slightly exposed to the contact holes 8b, a short circuit occurs between the gate electrodes 4b and the source and drain regions when the contact holes 8b are filled with the conductive material for contact.
To avoid the above described problems, it is necessary to provide sufficient distances between interconnect lines and between gate electrodes relative to a photomask alignment error and a contact hole diameter dimension error. This, however, prevents further size reduction of semiconductor devices.